[eagle] Re: Phased Array Concepts
matt at ettus.com
Thu Oct 25 22:03:30 PDT 2007
Long delayed response here ---
An inductor would not help. The problem occurs when the capacitance is
too big -- i.e. when the reactance approaches zero. An inductor would
allow us to cross zero reactance, but that's where we don't want to be
-- at zero reactance we create a short and very bad reflections.
PS I had to cancel my trip to the symposium at the last minute. Bob
will give my presentation. Have fun everyone.
John B. Stephensen wrote:
> Would an inductor in series with each varactor help? The total
> reactance can then vary from a positive value, through zero to a
> negative value so that a greater phase variation might be acheived
> with lower reflections.
> ----- Original Message ----- From: "Matt Ettus" <matt at ettus.com>
> To: <K3IO at verizon.net>
> Cc: "AMSAT Eagle" <Eagle at amsat.org>; "'Brian E. Gaffney'"
> <beg at bellatlantic.net>; "Daniel Schultz" <n8fgv at usa.net>
> Sent: Sunday, October 07, 2007 06:47 UTC
> Subject: [eagle] Re: Phased Array Concepts
>> I have the working simulation of the tapped delay line design. I did
>> all my sims with a delay line spacing of 30mm per element, or 0.3
>> wavelengths at 300 MHz. Some observations:
>> - Once the varactor capacitance gets high enough, you start to get
>> reflections which mess up the phasing. It happens to the elements
>> nearest to the generator (center of the array) first. At 300 MHz, you
>> get bad behavior at the center, first, and second elements if the
>> capacitance gets over about 0.8 pF. Going to a lower frequency will
>> allow for more capacitance, but you will need longer delay lines, and
>> will then end up with the same problem.
>> - The tap for getting the signal out may add capacitance of about the
>> same order of magnitude.
>> - The delay line needs to be long enough, or the caps all look like they
>> are in parallel.
>> - The center element will be common to all 12 strings, so some method of
>> splitting is necessary. This splitting will introduce a phase offset
>> which is not linear with the applied voltage, so it will need to be
>> compensated for by changing the length of the delay lines between the
>> center element and the first varactor.
>> - You can probably reduce the reflections by putting attenuators in the
>> delay lines, but these would make the DC biasing of the varactors more
>> I have attached my simulation. It was done in qucs, which runs on
>> linux. See qucs.sf.net or get it from your distribution.
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