[eagle] Re: Eagle Microwave AntennaArrays-- mechanical concepts
John B. Stephensen
kd6ozh at comcast.net
Sun Mar 25 19:44:51 PST 2007
I was thinking that the DCM output could be around 100 MHz to minimize
jitter. It consumes less power than a bank of DDSs. However, I still like
the analog phase shifters as that alternative may consume even less power.
----- Original Message -----
From: "Alan Bloom" <n1al at cds1.net>
To: "John B. Stephensen" <kd6ozh at comcast.net>
Cc: "Matt Ettus" <matt at ettus.com>; "AMSAT Eagle" <Eagle at amsat.org>
Sent: Monday, March 26, 2007 04:26 UTC
Subject: Re: [eagle] Re: Eagle Microwave AntennaArrays-- mechanical concepts
> This is an elegant and simple solution. However I'm worried that the
> DCM phase may not be accurate and stable enough. From the Xilinx
> "Virtex-4 data sheet: DC and Switching Characteristics", page 37, tables
> 45 and 46:
> Output clock synthesis period jitter: +/-100 ps
> Output clock phase offset between any DCM outputs: +/-140 ps
> With a 400 MHz clock, +/-140 ps is +/-20 degrees of phase. It doesn't
> seem like a 40 degree variation would be good enough for accurate array
> element phasing. Also the +/-100 ps jitter might adversely degrade the
> quality of the transmitted signal.
> However those are worst-case specifications. Perhaps phase innacuracy
> can be compensated by measuring the indivicual FPGAs we plan to use and
> including calibration tables in software. We would have to measure the
> parts over all environmental parameter ranges to be sure the calibrated
> values are stable and repeatable.
> Another solution might be to pick a lower clock frequency so that the
> innacuracy is a smaller percentage of a clock cycle. The tradeoff is
> that the IF image would be harder to filter out.
> This is a good enough idea that it is probably worth doing some
> investigation to see if it can be made to work. (Sorry, I'm not
> volunteering. :=)
> On Sun, 2007-03-25 at 16:06, John B. Stephensen wrote:
>> The big current spike is during start up and the static current
>> is low enough so that you can manage power dissiation. I wouldn't use
>> for the reciver as it must deal with multiple narrow-bandwidth signals.
>> downlink will be about 2 Mbaud BPSK so phase noise isn't a big issue in
>> generating low-frequency signals to be upconverted.
>> ----- Original Message -----
>> From: "Matt Ettus" <matt at ettus.com>
>> To: "AMSAT Eagle" <Eagle at amsat.org>
>> Sent: Sunday, March 25, 2007 21:40 UTC
>> Subject: [eagle] Re: Eagle Microwave Antenna Arrays-- mechanical concepts
>> > John B. Stephensen wrote:
>> >> The amount of power required by the FPGA depends on the number of
>> >> logic elements used and the speed of operation. Anything that isn't
>> >> clocked in the FPGA consumes almost no power so the thermal
>> >> dissipation is controlled by the logic designer.
>> > This is not true anymore. Small geometry devices (< 90nm) can consume
>> > a
>> > lot of static power.
>> >> DCMs require a lot
>> >> less power than an external DDS and an FPGA would be a good place to
>> >> put other logic.
>> > DCMs have horrible phase noise. You wouldn't want to use them for
>> > generating clocks for ADCs, DACs, LOs, or PLLs.
>> > Matt
>> > _______________________________________________
>> > Via the Eagle mailing list courtesy of AMSAT-NA
>> > Eagle at amsat.org
>> > http://amsat.org/mailman/listinfo/eagle
>> Via the Eagle mailing list courtesy of AMSAT-NA
>> Eagle at amsat.org
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