[eagle] Re: Eagle Microwave Antenna Arrays-- mechanical concepts

John B. Stephensen kd6ozh at comcast.net
Sun Mar 25 11:59:55 PST 2007


The amount of power required by the FPGA depends on the number of logic 
elements used and the speed of operation. Anything that isn't clocked in the 
FPGA consumes almost no power so the thermal dissipation is controlled by 
the logic designer. DCMs require a lot less power than an external DDS and 
an FPGA would be a good place to put other logic. A $15 FPGA has over a 
million equivalent gates and the DCMs are 1 or 2 percent of that. 
Essentially, this eliminates the power consumed by the ROMs and DACs in the 
DDS chips as there is no need to synthesize sine waves or to vary the 
frequency. Discrete clock distribution chips also perform the same function 
but a lot of power and PCB area would be cnsumed to drive them.

73,

John
KD6OZH

----- Original Message ----- 
From: "Alan Bloom" <n1al at cds1.net>
To: "John B. Stephensen" <kd6ozh at comcast.net>
Cc: <K3IO at verizon.net>; "AMSAT Eagle" <Eagle at amsat.org>
Sent: Sunday, March 25, 2007 05:40 UTC
Subject: Re: [eagle] Re: Eagle Microwave Antenna Arrays-- mechanical 
concepts


> On Sat, 2007-03-24 at 00:28, John B. Stephensen wrote:
>> The only disadvantage of the NCOs is the power required. Analog Devices
>> makes a quad  500 Msps DDS but it consumes up to 80 mW per channel and 
>> the
>> upconversion mixers will consume additional power. The MA/COM phase 
>> shifters
>> consume less than 50 mW per channel.
>
> 80 mW doesn't sound too bad for a signal chain with a 1W power
> amplifier.
>
>> However, NCOs aren't needed for the transmitter. The IF inputs could be
>> fixed-frequency square waves with adjustable time delays. Harmonics could 
>> be
>> cleaned up by low-pass filters preceeding the upconversion mixers. 
>> Spartan-3
>> FPGAs have up to 8 digital clock managers with 256-step time delays in 
>> 15-60
>> ps increments. A 15 ns maximum delay would allow a 360-degree phase shift 
>> at
>> frequencies as low as 67 MHz and the FPGA can be clocked at 200 MHz. 
>> Virtex
>> FPGAs run at 500 MHz and have more DCMs.
>
> But how much power do the FPGAs require?  Of course, it depends on what
> is programmed into them and the clock rate.  But I know that in some
> applications they require a heat sink, so it can be quite a lot (several
> watts) of power.
>
> Alan
>
> 



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